Many audio applications, such as audio analog to digital converters (ADCs) and audio encoder—decoders (CODECs), utilize a serial data port to transmit digitized audio data to other devices in a system. A typical audio serial data port outputs bits of a serial audio data (SDOUT) stream in response to an associated serial clock (SCLK) signal. In a stereo system, two channels of audio data are time-multiplexed onto the SDOUT stream with a left-right clock (LRCK) signal. Overall timing is controlled by a master clock (MCLK) signal. Advantageously, the utilization of serial ports minimizes the number of pins and associated on-chip driver circuitry.
A typical serial data port operates in either a master mode or a slave mode. In the master mode, the SCLK and LRCK clock signals are generated internally, in response to the received MCLK signal, and output to the destination of the SDOUT stream. In the slave (asynchronous) mode, the SCLK and LRCK clock signals are received from the destination of the SDOUT stream, and therefore may have an arbitrary phase relationships with the SDOUT stream.
In an ADC, the analog input signal is typically sampled on corresponding rising edges of an internal MCLK clock signal, while data are output on the following edges of the SCLK signal. One frequent problem experienced with ADC serial output ports is the coupling of digital noise onto the device substrate from the serial output driver driving the SDOUT output, especially when the SDOUT output is driving a relatively high load. For example, if a bit of the SDOUT stream is output on a falling edge of the SCLK clock signal occurring slightly before the next sample of the analog input is taken with the next rising edge of the MCLK signal, digital noise will couple into the ADC analog circuitry through the chip substrate or metal lines.
In the past, the problem of digital substrate noise generated by the SDOUT output driver has been addressed by re-timing the SCLK clock signal relative to the MCLK clock signal, such that the SDOUT output switching and analog input sampling operations are separated sufficiently in time to prevent digital noise in the substrate from being captured by the analog circuitry. However, in the slave mode, in which the SCLK signal is typically received with an arbitrary phase relationship with the external and/or internal MCLK signals, re-timing is often not possible. In particular, for higher frequency SCLK signals, the timing window between the SCLK signal and the internal MCLK signal may be too small to meet device operating parameters, such as set-up time. In some systems, the SCLK frequency may even exceed that of the internal MCLK signal, essentially excluding the re-timing approach to reducing digital noise coupling on-chip.
Utilizing an un-timed (asynchronous) serial port may be acceptable for DACs and lower-performance or lower-speed ADCs; however, for higher-speed, higher-performance ADCs, the problem of the coupling of digital noise generated by the serial output driver to other circuits on chip must be addressed. Consequently, improved techniques are required for reducing or eliminating digital noise generated by serial output drivers in high-performance applications, such as high-speed ADCs and CODECs. These techniques should be particular advantageous when utilized in devices operating in a slave mode in response to a received high frequency serial clock, although not necessarily limited thereto. Additionally, such techniques should be applicable to any type of mixed analog—digital device in which digital noise must be controlled, and especially to audio ADCs and CODECs.